circuit Alu : @[:@2.0]
  module Alu : @[:@3.2]
    input clock : Clock @[:@4.4]
    input reset : UInt<1> @[:@5.4]
    input io_fn : UInt<2> @[:@6.4]
    input io_a : UInt<4> @[:@6.4]
    input io_b : UInt<4> @[:@6.4]
    output io_result : UInt<4> @[:@6.4]
  
    node _T_16 = eq(UInt<1>("h0"), io_fn) @[Conditional.scala 37:30:@10.4]
    node _T_17 = add(io_a, io_b) @[Alu.scala 37:27:@12.6]
    node _T_18 = tail(_T_17, 1) @[Alu.scala 37:27:@13.6]
    node _T_20 = eq(UInt<1>("h1"), io_fn) @[Conditional.scala 37:30:@17.6]
    node _T_21 = sub(io_a, io_b) @[Alu.scala 38:27:@19.8]
    node _T_22 = asUInt(_T_21) @[Alu.scala 38:27:@20.8]
    node _T_23 = tail(_T_22, 1) @[Alu.scala 38:27:@21.8]
    node _T_25 = eq(UInt<2>("h2"), io_fn) @[Conditional.scala 37:30:@25.8]
    node _T_26 = or(io_a, io_b) @[Alu.scala 39:27:@27.10]
    node _T_28 = eq(UInt<2>("h3"), io_fn) @[Conditional.scala 37:30:@31.10]
    node _T_29 = and(io_a, io_b) @[Alu.scala 40:27:@33.12]
    node _GEN_0 = mux(_T_28, _T_29, UInt<1>("h0")) @[Conditional.scala 39:67:@32.10]
    node _GEN_1 = mux(_T_25, _T_26, _GEN_0) @[Conditional.scala 39:67:@26.8]
    node _GEN_2 = mux(_T_20, _T_23, _GEN_1) @[Conditional.scala 39:67:@18.6]
    node _GEN_3 = mux(_T_16, _T_18, _GEN_2) @[Conditional.scala 40:58:@11.4]
    node result = _GEN_3 @[Alu.scala 31:20:@8.4 Alu.scala 33:10:@9.4 Alu.scala 37:22:@14.6 Alu.scala 38:22:@22.8 Alu.scala 39:22:@28.10 Alu.scala 40:22:@34.12]
    io_result <= result @[Alu.scala 44:13:@36.4]
